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  • Parameter

LocoNet® Personal Use version definitions 1.0
All Copyrights and rights reserved, Digitrax 1997

In einem Argument können nur 7 Bit übertragen werden. Bestimmte Daten, wie beispielsweise die Lokadressen, umfassen aber mehr Bits, im Fall der Lokadresse sind es 11 Bits. Die Daten müssen dann auf zwei Argumente aufgeteilt werden: In einem Argument werden die höchstwertigen Stellen = ms-Bits (vom englischen most significant), in einem anderen die niedrigwertigsten Stellen = ls-Bits (von englischen least significant).

Bei Digitalzentralen wird in der Regel angegeben wie viele Loks gleichzeitig gesteuert werden können. Für jede gleichzeitig gesteuerte Lok gibt es in der Zentrale einen sog. Slot. In diesem wird der aktuelle Soll-Zustand (Lokadresse, Fahrstufen, Fahrtrichtung, Funktionen, usw.) einer Lok zwischengespeichert. Die Fahrregler greifen auf diese Slots zu und ändern dort den Soll-Zustand, sie senden also keine Befehle direkt an die Lok. Die Zentrale wiederum sendet jeweils die Daten aus den Slots über das Gleis.

• D7-SL_SPURGE
  • 1=SLOT purge en,ALSO adrSEL (INTERNAL use only, not seen on NET!)
    CONDN/CONUP: bit encoding-Control double linked Consist List

• D6-SL_CONUP
• D3-SL_CONDN
  • 11=LOGICAL MID CONSIST , Linked up AND down
  • 10=LOGICAL CONSIST TOP, Only linked downwards
  • 01=LOGICAL CONSIST SUB-MEMBER, Only linked upwards
  • 00=FREE locomotive, no CONSIST indirection/linking
    ALLOWS "CONSISTS of CONSISTS". Uplinked means that Slot SPD number is now SLOT adr of SPD/DIR and STATUS of consist. i.e. is an Indirect pointer. This Slot has same BUSY/ACTIVE bits as TOP of Consist. TOP is loco with SPD/DIR for whole consist. (top of list). BUSY/ACTIVE: bit encoding for SLOT activity

• D5-SL_BUSY
• D4-SL_ACTIVE
  • 11=IN_USE loco adr in SLOT -REFRESHED
  • 10=IDLE loco adr in SLOT, not refreshed
  • 01=COMMON loco adr IN SLOT, refreshed
  • 00=FREE SLOT, no valid DATA, not refreshed

• D2-SL_SPDEX
• D1-SL_SPD14
• D0-SL_SPD28
  • 010=14 step MODE
  • 001=28 step. Generate Trinary packets for this Mobile ADR
  • 000=28 step/ 3 BYTE PKT regular mode
  • 011=128 speed mode packets
  • 111=128 Step decoder, Allow Advanced DCC consisting
  • 100=28 Step decoder ,Allow Advanced DCC consisting

Der Zugriff auf das Programmiergleis erflogt als Spezial-Slot #124 ( $7C, 0x7C). Es ist eine voll asynchron geteilte System-Resource.
Zum Start eines Programmier-Tasks in Slot 124 schreiben. Es erfolgt unmittelbar ein LACK acknowledge, Das anzeigt, welche Programmierung erlaubt ist. Wenn ein gültiger Programmier-Task gestartet ist, wird beim letzten (asynchronen) Programmier-Abschluss ein Slot-Lesen <E7> von Slot 124 gesendet. Dies ist die abschliessende Task-Status-Antwort.

¹) Note that the <7F> code will occur in Operations Mode Read requests if the System is not configured for and has no Advanced Acknowlegement detection installed.. Operations Mode requests can be made and executed whilst a current Service Mode programming task is keeping the Programming track BUSY. If a Programming request is rejected, delay and resend the complete request later. Some readback operations can keep the Programming track busy for up to a minute. Multiple devices, throttles/PC's etc, can share and sequentially use the Programming track as long as they correctly interpret the response messages . Any Slot RD from the master will also contain the Programmer Busy status in bit 3 of the <TRK> byte.

²) This <E7> response is issued whenever a Programming task is completed. It echos most of the request information and returns the PSTAT status code to indicate how the task completed. If a READ was requested <DATA7> and <CVH> contain the returned data, if the PSTAT indicates a successful readback (typically =0). Note that if a Paged Read fails to detect a successful Page write acknowledge when first setting the Page register, the read will be aborted, showing no Write acknowledge flag D1=1

Power and transponding information is brought with the OPC_MULTI_SENSE opcode.

The system FAST clock and parameters are implemented in Slot#123 <7B>.
Use <EF> to write new clock information, Slot read of 0x7B,<BB><7B>.., will return current System clock information, and other throttles will update to this SYNC. Note that all attached display devices keep a current clock calculation based on this SYNC read value, i.e. devices MUST not continuously poll the clock SLOT to generate time, but use this merely to restore SYNC and follow current RATE etc. This clock slot is typically "pinged" or read SYNC'd every 70 to 100 seconds , by a single user, so all attached devices can synchronise any phase drifts. Upon seeing a SYNC read, all devices should reset their local sub-minute phase counter and invalidate the SYNC update ping generator.

Note that a 3 byte DCC track packet configured as:

<sync> ,<1011-1111>,<1000-D c b a > <ecb> 

is a DCC Broadcast Address to Stationary decoders. Broadcast LocoNet Switch adr is then

<SW2>=<0,0,a,D-1,1,1,1>, <SW1>=<0,1,1,1-1,0,c,b>

The DCC packet

<sync>,<1011-1111>,<1100-D c b a> <ecb>

is an Interrogation for all DS54's. This causes a 2 LocoNet <B1> messages encoding both Output state and Input state, for each sensor adr a/b/c encodes. Interrogate LocoNet Switch adr is

<SW2>=<0,0,a,1-0,1,1,1>, <SW1>= <0,1,1,1-1,0,c,b>

This is generated by DCS100 at power ON, and scans all 8 inputs of all DS54's.